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-- Company:
-- Engineer:
--
-- Create Date: 01:23:35 06/05/2013
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity main is
Port ( CLK_50M : in STD_LOGIC;
RF_START : in STD_LOGIC;
RF_UPDOWN : in STD_LOGIC_VECTOR (1 downto 0);
MOTOR : out STD_LOGIC_VECTOR (7 downto 0);
SEGMENT : out STD_LOGIC_VECTOR (6 downto 0));
end main;
architecture Behavioral of main is
signal rf_start_clk : std_logic;
signal rf_cnt : integer range -1 to 10 := 0;
signal rf_updown_clk : std_logic;
signal motor_clk : std_logic;
signal phase_cnt : std_logic_vector(2 downto 0);
signal phase_out : std_logic_vector(7 downto 0);
signal step_cnt : integer range 0 to 50000;
signal step_max : integer range 0 to 50000;
signal stop : std_logic;
signal start : std_logic;
begin
-----------------------------------------------------------------------------
--------------------------- Motor Clock Generator -------------------------------
----------------------------------------- MOTOR CLOCK : 50M/125000/2 = 200Hz
-----------------------------------------------------------------------------
process(start,CLK_50M)
variable cnt : integer range 0 to 125000;
begin
if start = '1' then
cnt := 0;
motor_clk <= '0';
elsif rising_edge(CLK_50M) then
if cnt >= 124999 then
cnt := 0;
motor_clk <= not motor_clk;
else
cnt := cnt + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------------
----------------------------- Motor Phase Count -----------------------------
-----------------------------------------------------------------------------
process(start,motor_clk,phase_cnt)
begin
if start = '1' then
phase_cnt <= (others => '0');
elsif rising_edge(motor_clk) then
phase_cnt <= phase_cnt+1;
end if;
end process;
-----------------------------------------------------------------------------
----------------------------- Motor Phase Out -------------------------------
--------------------------------------------------------------- 1-2상 여자 방식
-----------------------------------------------------------------------------
process(start,phase_cnt)
begin
if start = '1' then
phase_out <= (others => '0');
else
case phase_cnt is
when "000" =>
phase_out <= "10000001";
when "001" =>
phase_out <= "11000011";
when "010" =>
phase_out <= "01000010";
when "011" =>
phase_out <= "01100110";
when "100" =>
phase_out <= "00100100";
when "101" =>
phase_out <= "00111100";
when "110" =>
phase_out <= "00011000";
when "111" =>
phase_out <= "10011001";
when others =>
phase_out <= "00000000";
end case;
end if;
end process;
-----------------------------------------------------------------------------
--------------------- RF UPDOWN SWITCH CLOCK Generator ----------------------
-------------------------------------------------------------- 50M/5M/2 = 5Hz
-----------------------------------------------------------------------------
process(CLK_50M)
variable cnt : integer range 0 to 5000000;
begin
if rising_edge(CLK_50M) then
if cnt >= 4999999 then
cnt := 0;
rf_updown_clk <= not rf_updown_clk;
else
cnt := cnt + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------------
------------------------------ RF UP DOWN COUNT -----------------------------
-----------------------------------------------------------------------------
process(rf_updown_clk,RF_UPDOWN,stop,step_cnt)
begin
if rising_edge(rf_updown_clk) then
case RF_UPDOWN is
when "01" => rf_cnt <= rf_cnt + 1;
when "10" => rf_cnt <= rf_cnt - 1;
when others => null;
end case;
end if;
if rf_cnt < 0 then
rf_cnt <= 9;
elsif rf_cnt > 9 then
rf_cnt <= 0;
end if;
if stop='1' then
step_max <= rf_cnt * 400;
end if;
end process;
-----------------------------------------------------------------------------
--------------------------------- SEGMENT ---------------------------------
-----------------------------------------------------------------------------
process(rf_cnt,stop,step_cnt)
begin
if stop='1' then
case rf_cnt is
when 0 => SEGMENT <= "0111111";
when 1 => SEGMENT <= "0000110";
when 2 => SEGMENT <= "1011011";
when 3 => SEGMENT <= "1001111";
when 4 => SEGMENT <= "1100110";
when 5 => SEGMENT <= "1101101";
when 6 => SEGMENT <= "1111101";
when 7 => SEGMENT <= "0000111";
when 8 => SEGMENT <= "1111111";
when 9 => SEGMENT <= "1100111";
when others => SEGMENT <="0000000";
end case;
elsif stop='0' then
if step_cnt>0 and step_cnt<399 then
SEGMENT <= "0111111";
elsif step_cnt>=399 and step_cnt<799 then
SEGMENT <= "0000110";
elsif step_cnt>=799 and step_cnt<1199 then
SEGMENT <= "1011011";
elsif step_cnt>=1199 and step_cnt<1599 then
SEGMENT <= "1001111";
elsif step_cnt>=1599 and step_cnt<1999 then
SEGMENT <= "1100110";
elsif step_cnt>=1999 and step_cnt<2399 then
SEGMENT <= "1101101";
elsif step_cnt>=2399 and step_cnt<2799 then
SEGMENT <= "1111101";
elsif step_cnt>=2799 and step_cnt<3199 then
SEGMENT <= "0000111";
elsif step_cnt>=3199 and step_cnt<3599 then
SEGMENT <= "1111111";
elsif step_cnt=3599 then
SEGMENT <= "1100111";
end if;
end if;
end process;
-----------------------------------------------------------------------------
--------------------- RF START SWITCH CLOCK GENERATOR -----------------------
-------------------------------------- RF CLOCK : rf_clk : 50M/25000/2 = 1kHz
process(CLK_50M)
variable cnt : integer range 0 to 25000;
begin
if rising_edge(CLK_50M) then
if cnt >= 24999 then
cnt := 0;
rf_start_clk <= not rf_start_clk;
else
cnt := cnt + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------------
------------------------------ RF START SWITCH ------------------------------
-----------------------------------------------------------------------------
process(rf_start_clk)
variable cnt : integer range 0 to 100;
begin
if RF_START = '0' then
start <= '0';
cnt := 0;
elsif rising_edge(rf_start_clk) then
cnt := cnt + 1;
if cnt = 100 then
start <= '1';
cnt := 0;
end if;
end if;
end process;
---------------------------- 1바퀴만 회전 후,정지 -----------------------------
process(start,motor_clk,step_cnt,stop)
begin
if start='1' then
stop <= '0'; step_cnt <=0;
elsif rising_edge(motor_clk) then
if step_cnt >= (step_max-1) then
stop <= '1';
step_cnt <= 0;
else
step_cnt <= step_cnt + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------------
MOTOR(7) <= phase_out(7) when stop = '0' else '0';
MOTOR(6) <= phase_out(6) when stop = '0' else '0';
MOTOR(5) <= phase_out(5) when stop = '0' else '0';
MOTOR(4) <= phase_out(4) when stop = '0' else '0';
MOTOR(3) <= phase_out(3) when stop = '0' else '0';
MOTOR(2) <= phase_out(2) when stop = '0' else '0';
MOTOR(1) <= phase_out(1) when stop = '0' else '0';
MOTOR(0) <= phase_out(0) when stop = '0' else '0';
-----------------------------------------------------------------------------
end Behavioral;
result.mp4